List Of Intel Microprocessors - Intel Computer Chips

This generational and chronological list of Intel processors attempts to present all of Intel's processors from the pioneering 4-bit 4004 (1971) to the present high-end offerings, which include the 64-bit Itanium 2 (2002), Intel Core i7, and Xeon E3 and E5 series processors (2015). Concise technical data is given for each product.

The 4-bit processors

source : wccftech.com

Intel 4004

First microprocessor (single-chip IC processor)

Clock rate 740 kHz
0.07 MIPS
Bus width 4 bits (multiplexed address/data due to limited pins)
PMOS
2,300 transistors at 10Â Î¼m
Addressable Memory 640Â bytes
Program Memory 4Â KB
Originally designed to be used in Busicom calculator

MCS-4 Family:

4004 â€" CPU
4001 â€" ROM & 4-bit Port
4002 â€" RAM & 4-bit Port
4003 â€" 10-bit Shift Register
4008 â€" Memory+I/O Interface
4009 â€" Memory+I/O Interface
Introduced November 15, 1971
4211 â€" General Purpose Byte I/O Port
4265 â€" Programmable General Purpose I/O Device
4269 â€" Programmable Keyboard Display Device
4289 â€" Standard Memory Interface for MCS-4/40
4308 â€" 8192-bit (1024 Ã— 8) ROM w/ 4-bit I/O Ports
4316 â€" 16384-bit (2048 Ã— 8) Static ROM
4702 â€" 2048-bit (256 Ã— 8) EPROM
4801 â€" 5.185Â MHz Clock Generator Crystal for 4004/4201A or 4040/4201A
Introduced 1971

Intel 4040:

Introduced in 1974 by Intel.
Clock speed was 740Â kHz (same as the 4004 microprocessor).
3000 transistors.
Interrupt features were available.
Programmable memory size: 8KB.
640 bytes of data memory.
24 pin DIP

The 8-bit processors

source : en.community.dell.com

8008

Introduced April 1, 1972
Clock rate 500Â kHz (8008â€"1: 800Â kHz)
0.05 MIPS
Bus width 8 bits (multiplexed address/data due to limited pins)
Enhancement load PMOS logic
3,500 transistors at 10Â Î¼m
Addressable memory 16 KB
Typical in early 8-bit microcomputers, dumb terminals, general calculators, bottling machines
Developed in tandem with 4004
Originally intended for use in the Datapoint 2200 microcomputer
Key volume deployment in Texas Instruments 742 microcomputer in >3,000 Ford dealerships

8080

Introduced April 1, 1974
Clock rate 2Â MHz (very rare 8080B: 3Â MHz)
0.29 MIPS
Data bus width 8 bits, Address bus 16 bits
Enhancement load NMOS logic
4500 transistors at 6Â Î¼m
Assembly language downward compatible with 8008
Addressable memory 64 KB
Up to 10Ã— the performance of the 8008
Used in the Altair 8800, Traffic light controller, cruise missile
Required six support chips versus 20 for the 8008

8085

Introduced March 1976
Clock rate 3Â MHz
0.37 MIPS
Data bus width 8 bits, Address bus 16 bits
Depletion load NMOS logic
6500 transistors at 3Â Î¼m
Binary compatible downward with the 8080
Used in Toledo scales. Also used as a computer peripheral controller â€" modems, hard disks, printers, etc.
CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.

Microcontrollers

source : wccftech.com

They are ICs with CPU, RAM, ROM (or PROM or EPROM), I/O Ports, Timers & Interrupts

Intel 8048

Single accumulator Harvard architecture

MCS-48 family:

8020 â€" Single-Component 8-bit Microcontroller
8021 â€" Single-Component 8-bit Microcontroller
8022 â€" Single-Component 8-bit Microcontroller With On-Chip A/D Converter
8035 â€" Single-Component 8-bit Microcontroller
8039 â€" Single-Component 8-bit Microcontroller
8040 â€" Single-Component 8-bit Microcontroller
8041 â€" Universal Peripheral Interface 8-bit Slave Microcontroller
8641 â€" Universal Peripheral Interface 8-bit Slave Microcontroller
8741 â€" Universal Peripheral Interface 8-bit Slave Microcontroller
8042 â€" Universal Peripheral Interface 8-bit Slave Microcontroller
8742 â€" Universal Peripheral Interface 8-bit Slave Microcontroller
8243 â€" Input/Output Expander
8244 â€" ASIC (NTSC)
8245 â€" ASIC (PAL)
8048 â€" Single-Component 8-bit Microcontroller
8048 â€" Single-Component 8-bit Microcontroller
8748 â€" Single-Component 8-bit Microcontroller
8048 â€" Single-Component 8-bit Microcontroller
8049 â€" Single-Component 8-bit Microcontroller
8749 â€" Single-Component 8-bit Microcontroller
8050 â€" Single-Component 8-bit Microcontroller

Intel 8051

Single accumulator Harvard architecture

MCS-51 Family:

8031 â€" 8-bit Control-Oriented Microcontroller
8032 â€" 8-bit Control-Oriented Microcontroller
8044 â€" High Performance 8-bit Microcontroller
8344 â€" High Performance 8-bit Microcontroller
8744 â€" High Performance 8-bit Microcontroller
8051 â€" 8-bit Control-Oriented Microcontroller
8052 â€" 8-bit Control-Oriented Microcontroller
8054 â€" 8-bit Control-Oriented Microcontroller
8058 â€" 8-bit Control-Oriented Microcontroller
8351 â€" 8-bit Control-Oriented Microcontroller
8352 â€" 8-bit Control-Oriented Microcontroller
8354 â€" 8-bit Control-Oriented Microcontroller
8358 â€" 8-bit Control-Oriented Microcontroller
8751 â€" 8-bit Control-Oriented Microcontroller
8752 â€" 8-bit Control-Oriented Microcontroller
8754 â€" 8-bit Control-Oriented Microcontroller
8758 â€" 8-bit Control-Oriented Microcontroller

Intel 80151

Single accumulator Harvard architecture

MCS-151 Family:

80151 â€" High Performance 8-bit Control-Oriented Microcontroller
83151 â€" High Performance 8-bit Control-Oriented Microcontroller
87151 â€" High Performance 8-bit Control-Oriented Microcontroller
80152 â€" High Performance 8-bit Control-Oriented Microcontroller
83152 â€" High Performance 8-bit Control-Oriented Microcontroller

Intel 80251

Single accumulator Harvard architecture

MCS-251 Family:

80251 â€" 8/16/32-bit Microcontroller
80252 â€" 8/16/32-bit Microcontroller
80452 â€" 8/16/32-bit Microcontroller
83251 â€" 8/16/32-bit Microcontroller
87251 â€" 8/16/32-bit Microcontroller
87253 â€" 8/16/32-bit Microcontroller

MCS-96 Family

8094 â€" 16-bit Microcontroller (48-Pin ROMLess Without A/D)
8095 â€" 16-bit Microcontroller (48-Pin ROMLess With A/D)
8096 â€" 16-bit Microcontroller (68-Pin ROMLess Without A/D)
8097 â€" 16-bit Microcontroller (68-Pin ROMLess With A/D)
8394 â€" 16-bit Microcontroller (48-Pin With ROM Without A/D)
8395 â€" 16-bit Microcontroller (48-Pin With ROM With A/D)
8396 â€" 16-bit Microcontroller (68-Pin With ROM Without A/D)
8397 â€" 16-bit Microcontroller (68-Pin With ROM With A/D)
8794 â€" 16-bit Microcontroller (48-Pin With EROM Without A/D)
8795 â€" 16-bit Microcontroller (48-Pin With EROM With A/D)
8796 â€" 16-bit Microcontroller (68-Pin With EROM Without A/D)
8797 â€" 16-bit Microcontroller (68-Pin With EROM With A/D)
8098 â€" 16-bit Microcontroller
8398 â€" 16-bit Microcontroller
8798 â€" 16-bit Microcontroller
80196 â€" 16-bit Microcontroller
83196 â€" 16-bit Microcontroller
87196 â€" 16-bit Microcontroller
80296 â€" 16-bit Microcontroller

The bit-slice processor

source : www.dailytech.com

3000 Family

Introduced in the third quarter of 1974, these components used bipolar Schottky transistors. Each component implemented two bits of a processor function; packages could be interconnected to build a processor with any desired word length. Members of the family:

3001 â€" Microcontrol Unit
3002 â€" 2-bit Arithmetic Logic Unit slice
3003 â€" Look-ahead Carry Generator
3205 â€" High-performance 1 of 8 Binary Decoder
3207 â€" Quad Bipolar-to-MOS Level Shifter and Driver
3208 â€" Hex Sense Amp and Latch for MOS Memories
3210 â€" TTL-to-MOS Level Shifter and High Voltage Clock Driver
3211 â€" ECL-to-MOS Level Shifter and High Voltage Clock Driver
3212 â€" Multimode Latch Buffer
3214 â€" Interrupt Control Unit
3216 â€" Parallel, Inverting Bi-Directional Bus Driver
3222 â€" Refresh Controller for 4K NMOS DRAMs
3226 â€" Parallel, Inverting Bi-Directional Bus Driver
3232 â€" Address Multiplexer and Refresh Counter for 4K DRAMs
3242 â€" Address Multiplexer and Refresh Counter for 16K DRAMs
3245 â€" Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
3246 â€" Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
3404 â€" High-performance 6-bit Latch
3408 â€" Hex Sense Amp and Latch for MOS Memories
3505 - Next generation processor

Bus width 2*n bits data/address (depending on number n of slices used)

The 16-bit processors: MCS-86 family

source : www.preventheadacheguide.info

8086

Introduced June 8, 1978
Clock rates:
- 5Â MHz, 0.33 MIPS
- 8Â MHz, 0.66 MIPS
- 10Â MHz, 0.75 MIPS
The memory is divided into odd and even banks. It accesses both banks concurrently to read 16 bits of data in one clock cycle
Data bus width 16 bits, Address bus 20 bits
29000 transistors at 3Â Î¼m
Addressable memory 1Â megabyte
Up to 10Ã— the performance of 8080
First used in the Compaq Deskpro IBM PC-compatible computers. Later used in portable computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular IBM PC-compatible (predating the IBM PS/2 line).
Used segment registers to access more than 64 KB of data at once, which many programmers complained made their work excessively difficult.
The first x86 CPU.
Later renamed the iAPX 86

8088

Introduced June 1, 1979
Clock rates:
- 4.77Â MHz, 0.33 MIPS
- 8Â MHz, 0.66 MIPS
Internal architecture 16 bits
External data bus Width 8 bits, Address bus 20 bits
29000 transistors 29,000 at 3Â Î¼m
Addressable memory 1Â megabyte
Identical to 8086 except for its 8-bit external bus (hence an 8 instead of a 6 at the end); identical Execution Unit (EU), different Bus Interface Unit (BIU)
Used in IBM PC and PC-XT and compatibles
Later renamed the iAPX 88

80186

Introduced 1982
Clock rates
- 6Â MHz, > 1 MIPS
55000 transistors
Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor (these were at fixed addresses which differed from the IBM PC, although it was used by several PC compatible vendors such as Australian company Cleveland).
Added a few opcodes and exceptions to the 8086 design, otherwise identical instruction set to 8086 and 8088
- BOUND, ENTER, LEAVE
- INS, OUTS
- IMUL imm, PUSH imm, PUSHA, POPA
- RCL/RCR/ROL/ROR/SHL/SHR/SAL/SAR reg,imm
Address calculation and shift operations are faster than 8086
Used mostly in embedded applications â€" controllers, point-of-sale systems, terminals, and the like
Used in several non-PC compatible DOS computers including RM Nimbus, Tandy 2000, and CP/M 86 Televideo PM16 server
Later renamed to iAPX 186

80188

A version of the 80186 with an 8-bit external data bus
Later renamed the iAPX 188

80286

Introduced February 2, 1982
Clock rates:
- 6Â MHz, 0.9 MIPS
- 8Â MHz, 10Â MHz, 1.5 MIPS
- 12.5Â MHz, 2.66 MIPS
- 16Â MHz, 20Â MHz and 25Â MHz available.
Data bus width: 16 bits, Address bus 24 bits
Included memory protection hardware to support multitasking operating systems with per-process address space.
134,000 transistors 134,000 at 1.5Â Î¼m
Addressable memory 16Â MB
Added protected-mode features to 8086 with essentially the same instruction set
3â€"6Ã— the performance of the 8086
Widely used in IBM-PC AT and AT clones contemporary to it.

32-bit processors: the non-x86 microprocessors

source : commons.wikimedia.org

iAPX 432

Introduced January 1, 1981 as Intel's first 32-bit microprocessor
Multi-chip CPU
Object/capability architecture
Microcoded operating system primitives
One terabyte virtual address space
Hardware support for fault tolerance
Two-chip General Data Processor (GDP), consists of 43201 and 43202
43203 Interface Processor (IP) interfaces to I/O subsystem
43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
43205 Memory Control Unit (MCU)
Architecture and execution unit internal data base paths 32 bit
Clock rates:
- 5Â MHz
- 7Â MHz
- 8Â MHz

i960 a.k.a. 80960

Introduced April 5, 1988
RISC-like 32-bit architecture
Predominantly used in embedded systems
Evolved from the capability processor developed for the BiiN joint venture with Siemens
Many variants identified by two-letter suffixes.

i860 a.k.a. 80860

Introduced February 26, 1989
RISC 32/64-bit architecture, with floating point pipeline characteristics very visible to programmer
Used in the Intel iPSC/860 Hypercube parallel supercomputer
Mid-life kicker in the i870 processor (primarily a speed bump, some refinement/extension of instruction set)
Used in the Intel Delta massively parallel supercomputer prototype, emplaced at California Institute of Technology
Used in the Intel Paragon massively parallel supercomputer, emplaced at Sandia National Laboratory

XScale

Introduced August 23, 2000
32-bit RISC microprocessor based on the ARM architecture
Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.

32-bit processors: the 80386 range

source : www.pcworld.com

80386DX

Introduced October 17, 1985
Clock rates:
- 16Â MHz, 5 MIPS
- 20Â MHz, 6 to 7 MIPS, introduced February 16, 1987
- 25Â MHz, 7.5 MIPS, introduced April 4, 1988
- 33Â MHz, 9.9 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced April 10, 1989
Data bus width 32 bits, Address bus 32 bits
275,000 transistors 275,000 at 1Â Î¼m
Addressable memory 4Â KB
Virtual memory 64 KB
First x86 chip to handle 32-bit data sets
Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required at the time by Xenix and Unix. This memory capability spurred the development and availability of OS/2 and is a fundamental requirement for modern operating systems like Linux, Windows, and macOS.
First used by Compaq in the Deskpro 386. Used in desktop computing
Unlike the DX naming convention of the 486 chips, it had no math co-processor.
Later renamed Intel386 DX

80386SX

Introduced June 16, 1988
Clock rates:
- 16Â MHz, 2.5 MIPS
- 20Â MHz, 3.1 MIPS, introduced January 25, 1989
- 25Â MHz, 3.9 MIPS, introduced January 25, 1989
- 33Â MHz, 5.1 MIPS, introduced October 26, 1992
Internal architecture 32 bits
External data bus width 16 bits
External address bus width 24 bits
275,000 transistors at 1Â Î¼m
Addressable memory 16Â KB
Virtual memory 32Â KB
Narrower buses enable low-cost 32-bit processing
Used in entry-level desktop and portable computing
No math co-processor
No commercial software used for protected mode or virtual storage for many years
Later renamed Intel386 SX

80376

Introduced January 16, 1989; discontinued June 15, 2001
Variant of 386SX intended for embedded systems
No "real mode", starts up directly in "protected mode"
Replaced by much more successful 80386EX from 1994

80386SL

Introduced October 15, 1990
Clock rates:
- 20Â MHz, 4.21 MIPS
- 25Â MHz, 5.3 MIPS, introduced September 30, 1991
Internal architecture 32 bits
External bus width 16 bits
855,000 transistors at 1Â Î¼m
Addressable memory 4Â KB
Virtual memory 10 KB
First chip specifically made for portable computers because of low power consumption of chip
Highly integrated, includes cache, bus, and memory controllers

80386EX

Introduced August 1994
Variant of 80386SX intended for embedded systems
Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
On-chip peripherals:
- Clock and power management
- Timers/counters
- Watchdog timer
- Serial I/O units (sync and async) and parallel I/O
- DMA
- RAM refresh
- JTAG test logic
Significantly more successful than the 80376
Used aboard several orbiting satellites and microsatellites
Used in NASA's FlightLinux project

32-bit processors: the 80486 range

source : www.intel.com

80486DX

Introduced April 10, 1989
Clock rates:
- 25Â MHz, 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
- 33Â MHz, 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced May 7, 1990
- 50Â MHz, 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced June 24, 1991
Bus width 32 bits
1.2 million transistors at 1Â Î¼m; the 50Â MHz was at 0.8Â Î¼m
Addressable memory 4Â GB
Virtual memory 1 TB
Level 1 cache of 8 KB on chip
Math coprocessor on chip
50Ã— performance of the 8088
Officially named Intel486 DX
Used in Desktop computing and servers
Family 4 model 1

80486SX

Introduced April 22, 1991
Clock rates:
- 16Â MHz, 13 MIPS
- 20Â MHz, 16.5 MIPS, introduced September 16, 1991
- 25Â MHz, 20 MIPS (12 SPECint92), introduced September 16, 1991
- 33Â MHz, 27 MIPS (15.86 SPECint92), introduced September 21, 1992
Bus width 32 bits
1.185 million transistors at 1Â Î¼m and 900,000 at 0.8Â Î¼m
Addressable memory 4Â GB
Virtual memory 1 TB
Identical in design to 486DX but without a math coprocessor. The first version was an 80486DX with disabled math coprocessor in the chip and different pin configuration. If the user needed math coprocessor capabilities, he must add 487SX which was actually an 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 effectively turned on
Officially named Intel486 SX
Used in low-cost entry to 486 CPU desktop computing, as well as extensively in low cost mobile computing.
Upgradable with the Intel OverDrive processor
Family 4 model 2

80486DX2

Introduced March 3, 1992

Runs at twice the speed of the external bus (FSB). Fits in Socket 3

Clock rates:
- 40Â MHz
- 50Â MHz
- 66Â MHz
Officially named Intel486 DX2
Family 4 model 3

80486SL

Introduced November 9, 1992
Clock rates:
- 20Â MHz, 15.4 MIPS
- 25Â MHz, 19 MIPS
- 33Â MHz, 25 MIPS
Bus width 32 bits
1.4 million transistors at 0.8Â Î¼m
Addressable memory 4Â GB
Virtual memory 1 TB
Officially named Intel486 SL
Used in notebook computers
Family 4 model 4

80486DX4

Introduced March 7, 1994
Clock rates:
- 75Â MHz, 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
- 100Â MHz, 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)
1.6 million transistors at 0.6Â Î¼m
Bus width 32 bits
Addressable memory 4Â GB
Virtual memory 64 TB
Pin count 168 PGA Package, 208 sq ftP Package
Officially named Intel486 DX4
Used in high performance entry-level desktops and value notebooks
Family 4 model 8

32-bit processors: P5 microarchitecture

source : www.lowyat.net

Original Pentium

Bus width 64 bits
System bus clock rate 60 or 66Â MHz
Address bus 32 bits
Addressable Memory 4Â GB
Virtual Memory 1 TB
Superscalar architecture
Runs on 3.3 Volts (except the very first generation "P5")
Used in desktops
8 KB of instruction cache
8 KB of data cache
P5 â€" 0.8Â Î¼m process technology
- Introduced March 22, 1993
- 3.1 million transistors
- The only Pentium to run on 5 Volts
- Socket 4 273 pin PGA processor package
- Package dimensions 2.16â€³ Ã— 2.16â€³
- Family 5 model 1
- Variants
  - 60Â MHz, 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)
  - 66Â MHz, 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)
P54 â€" 0.6Â Î¼m process technology
- Socket 5 296/320 pin PGA package
- 3.2 million transistors
- Variants
  - 75Â MHz, 126.5 MIPS (2.31 SPECint95, 2.02 SPECfp95 on Gateway P5 256K L2)
    - Introduced October 10, 1994
  - 90, 100Â MHz, 149.8 and 166.3 MIPS respectively (2.74 SPECint95, 2.39 SPECfp95 on Gateway P5 256K L2 and 3.30 SPECint95, 2.59 SPECfp95 on Xpress 1ML2 respectively)
    - Introduced March 7, 1994
P54CQS â€" 0.35Â Î¼m process technology
- Socket 5 296/320 pin PGA package
- 320 million transistors
- Variants
  - 120Â MHz, 203 MIPS (3.72 SPECint95, 2.81 SPECfp95 on Xpress 1MB L2)
    - Introduced March 27, 1995
P54CS â€" 0.35Â Î¼m process technology
- 3.3 million transistors
- 90Â mmÂ² die size
- Family 5 model 2
- Variants
- Socket 5 296/320 pin PGA package
  - 133Â MHz, 218.9 MIPS (4.14 SPECint95, 3.12 SPECfp95 on Xpress 1MB L2)
    - Introduced June 12, 1995
  - 150, 166Â MHz, 230 and 247 MIPS respectively
    - Introduced January 4, 1996
- Socket 7 296/321 pin PGA package
  - 200Â MHz, 270 MIPS (5.47 SPECint95, 3.68 SPECfp95)
    - Introduced June 10, 1996

Pentium with MMX Technology

P55C â€" 0.35Â Î¼m process technology
- Introduced January 8, 1997
- Intel MMX (instruction set) support
- Socket 7 296/321 pin PGA (pin grid array) package
- 16 KB L1 instruction cache
- 16 KB L1 data cache
- 4.5 million transistors
- System bus clock rate 66Â MHz
- Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
- Variants
  - 166, 200Â MHz Introduced January 8, 1997
  - 233Â MHz Introduced June 2, 1997
  - 133Â MHz (Mobile)
  - 166, 266Â MHz (Mobile) Introduced January 12, 1998
  - 200, 233Â MHz (Mobile) Introduced September 8, 1997
  - 300Â MHz (Mobile) Introduced January 7, 1999

32-bit processors: P6/Pentium M microarchitecture

Pentium Pro

Introduced November 1, 1995
Precursor to Pentium II and III
Primarily used in server systems
Socket 8 processor package (387 pins) (Dual SPGA)
5.5 million transistors
Family 6 model 1
0.6Â Î¼m process technology
- 16 KB L1 cache
- 256 KB integrated L2 cache
- 60Â MHz system bus clock rate
- Variants
  - 150Â MHz
0.35Â Î¼m process technology, or 0.35Â Î¼m CPU with 0.6Â Î¼m L2 cache
- 5.5 million transistors
- 512 KB or 256 KB integrated L2 cache
- 60 or 66Â MHz system bus clock rate
- Variants
  - 166Â MHz (66Â MHz bus clock rate, 512 KB 0.35Â Î¼m cache) Introduced November 1, 1995
  - 180Â MHz (60Â MHz bus clock rate, 256 KB 0.6Â Î¼m cache) Introduced November 1, 1995
  - 200Â MHz (66Â MHz bus clock rate, 256 KB 0.6Â Î¼m cache) Introduced November 1, 1995
  - 200Â MHz (66Â MHz bus clock rate, 512 KB 0.35Â Î¼m cache) Introduced November 1, 1995
  - 200Â MHz (66Â MHz bus clock rate, 1Â MB 0.35Â Î¼m cache) Introduced August 18, 1997

Pentium II

Introduced May 7, 1997
Pentium Pro with MMX and improved 16-bit performance
242-pin Slot 1 (SEC) processor package
Voltage identification pins
7.5 million transistors
32 KB L1 cache
512 KB â€Š¹â„₂ bandwidth external L2 cache
The only Pentium II that did not have the L2 cache at â€Š¹â„₂ bandwidth of the core was the Pentium II 450 PE.
Klamath â€" 0.35Â Î¼m process technology (233, 266, 300Â MHz)
- 66Â MHz system bus clock rate
- Family 6 model 3
- Variants
  - 233, 266, 300Â MHz Introduced May 7, 1997
Deschutes â€" 0.25Â Î¼m process technology (333, 350, 400, 450Â MHz)
- Introduced January 26, 1998
- 66Â MHz system bus clock rate (333Â MHz variant), 100Â MHz system bus clock rate for all subsequent models
- Family 6 model 5
- Variants
  - 333Â MHz Introduced January 26, 1998
  - 350, 400Â MHz Introduced April 15, 1998
  - 450Â MHz Introduced August 24, 1998
  - 233, 266Â MHz (Mobile) Introduced April 2, 1998
  - 333Â MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998
  - 300Â MHz (Mobile) Introduced September 9, 1998
  - 333Â MHz (Mobile) Introduced January 25, 1999

Celeron (Pentium II-based)

Covington â€" 0.25Â Î¼m process technology
- Introduced April 15, 1998
- 242-pin Slot 1 SEPP (Single Edge Processor Package)
- 7.5 million transistors
- 66Â MHz system bus clock rate
- Slot 1
- 32 KB L1 cache
- No L2 cache
- Variants
  - 266Â MHz Introduced April 15, 1998
  - 300Â MHz Introduced June 9, 1998
Mendocino â€" 0.25Â Î¼m process technology
- Introduced August 24, 1998
- 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package
- 19 million transistors
- 66Â MHz system bus clock rate
- Slot 1, Socket 370
- 32 KB L1 cache
- 128 KB integrated cache
- Family 6 model 6
- Variants
  - 300, 333Â MHz Introduced August 24, 1998
  - 366, 400Â MHz Introduced January 4, 1999
  - 433Â MHz Introduced March 22, 1999
  - 466Â MHz
  - 500Â MHz Introduced August 2, 1999
  - 533Â MHz Introduced January 4, 2000
  - 266Â MHz (Mobile)
  - 300Â MHz (Mobile)
  - 333Â MHz (Mobile) Introduced April 5, 1999
  - 366Â MHz (Mobile)
  - 400Â MHz (Mobile)
  - 433Â MHz (Mobile)
  - 450Â MHz (Mobile) Introduced February 14, 2000
  - 466Â MHz (Mobile)
  - 500Â MHz (Mobile) Introduced February 14, 2000

Pentium II Xeon (chronological entry)

Introduced June 29, 1998
See main entry

Pentium III

Katmai â€" 0.25Â Î¼m process technology
- Introduced February 26, 1999
- Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
- 9.5 million transistors
- 512 KB â€Š¹â„₂ bandwidth L2 External cache
- 242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
- System Bus clock rate 100Â MHz, 133Â MHz (B-models)
- Slot 1
- Family 6 model 7
- Variants
  - 450, 500Â MHz Introduced February 26, 1999
  - 550Â MHz Introduced May 17, 1999
  - 600Â MHz Introduced August 2, 1999
  - 533, 600Â MHz Introduced (133Â MHz bus clock rate) September 27, 1999
Coppermine â€" 0.18Â Î¼m process technology
- Introduced October 25, 1999
- 28.1 million transistors
- 256 KB Advanced Transfer L2 Cache (Integrated)
- 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package
- System Bus clock rate 100Â MHz (E-models), 133Â MHz (EB models)
- Slot 1, Socket 370
- Family 6 model 8
- Variants
  - 500Â MHz (100Â MHz bus clock rate)
  - 533Â MHz
  - 550Â MHz (100Â MHz bus clock rate)
  - 600Â MHz
  - 600Â MHz (100Â MHz bus clock rate)
  - 650Â MHz (100Â MHz bus clock rate) Introduced October 25, 1999
  - 667Â MHz Introduced October 25, 1999
  - 700Â MHz (100Â MHz bus clock rate) Introduced October 25, 1999
  - 733Â MHz Introduced October 25, 1999
  - 750, 800Â MHz (100Â MHz bus clock rate) Introduced December 20, 1999
  - 850Â MHz (100Â MHz bus clock rate) Introduced March 20, 2000
  - 866Â MHz Introduced March 20, 2000
  - 933Â MHz Introduced May 24, 2000
  - 1000Â MHz Introduced March 8, 2000 (not widely available at time of release)
  - 1100Â MHz
  - 1133Â MHz (first version recalled, later re-released)
  - 400, 450, 500Â MHz (Mobile) Introduced October 25, 1999
  - 600, 650Â MHz (Mobile) Introduced January 18, 2000
  - 700Â MHz (Mobile) Introduced April 24, 2000
  - 750Â MHz (Mobile) Introduced June 19, 2000
  - 800, 850Â MHz (Mobile) Introduced September 25, 2000
  - 900, 1000Â MHz (Mobile) Introduced March 19, 2001
Tualatin â€" 0.13Â Î¼m process technology
- Introduced July 2001
- 28.1 million transistors
- 32 KB L1 cache
- 256 KB or 512 KB Advanced Transfer L2 cache (integrated)
- 370-pin FC-PGA2 (flip-chip pin grid array) package
- 133Â MHz system bus clock rate
- Socket 370
- Family 6 model 11
- Variants
  - 1133Â MHz (256 KB L2)
  - 1133Â MHz (512 KB L2)
  - 1200Â MHz
  - 1266Â MHz (512 KB L2)
  - 1333Â MHz
  - 1400Â MHz (512 KB L2)

Pentium II and III Xeon

PII Xeon
- Variants
  - 400Â MHz Introduced June 29, 1998
  - 450Â MHz (512 KB L2 Cache) Introduced October 6, 1998
  - 450Â MHz (1Â MB and 2Â MB L2 Cache) Introduced January 5, 1999
PIII Xeon
- Introduced October 25, 1999
- 9.5 million transistors at 0.25Â Î¼m or 28 million at 0.18Â Î¼m
- L2 cache is 256 KB, 1Â MB, or 2Â MB Advanced Transfer Cache (Integrated)
- Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
- System Bus clock rate 133Â MHz (256 KB L2 cache) or 100Â MHz (1â€"2Â MB L2 cache)
- System Bus width 64 bits
- Addressable memory 64Â GB
- Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1â€"2Â MB L2)
- Family 6 model 10
- Variants
  - 500Â MHz (0.25Â Î¼m process) Introduced March 17, 1999
  - 550Â MHz (0.25Â Î¼m process) Introduced August 23, 1999
  - 600Â MHz (0.18Â Î¼m process, 256 KB L2 cache) Introduced October 25, 1999
  - 667Â MHz (0.18Â Î¼m process, 256 KB L2 cache) Introduced October 25, 1999
  - 733Â MHz (0.18Â Î¼m process, 256 KB L2 cache) Introduced October 25, 1999
  - 800Â MHz (0.18Â Î¼m process, 256 KB L2 cache) Introduced January 12, 2000
  - 866Â MHz (0.18Â Î¼m process, 256 KB L2 cache) Introduced April 10, 2000
  - 933Â MHz (0.18Â Î¼m process, 256 KB L2 cache)
  - 1000Â MHz (0.18Â Î¼m process, 256 KB L2 cache) Introduced August 22, 2000
  - 700Â MHz (0.18Â Î¼m process, 1â€"2Â MB L2 cache) Introduced May 22, 2000

Celeron (Pentium III Coppermine-based)

Coppermine-128, 0.18Â Î¼m process technology
- Introduced March, 2000
- Streaming SIMD Extensions (SSE)
- Socket 370, FC-PGA processor package
- 28.1 million transistors
- 66Â MHz system bus clock rate, 100Â MHz system bus clock rate from January 3, 2001
- 32 kB L1 cache
- 128 kB Advanced Transfer L2 cache
- Family 6 model 8
- Variants
  - 533Â MHz
  - 566Â MHz
  - 600Â MHz
  - 633, 667, 700Â MHz Introduced June 26, 2000
  - 733, 766Â MHz Introduced November 13, 2000
  - 800Â MHz Introduced January 3, 2001
  - 850Â MHz Introduced April 9, 2001
  - 900Â MHz Introduced July 2, 2001
  - 950, 1000, 1100Â MHz Introduced August 31, 2001
  - 550Â MHz (Mobile)
  - 600, 650Â MHz (Mobile) Introduced June 19, 2000
  - 700Â MHz (Mobile) Introduced September 25, 2000
  - 750Â MHz (Mobile) Introduced March 19, 2001
  - 800Â MHz (Mobile)
  - 850Â MHz (Mobile) Introduced July 2, 2001
  - 600Â MHz (LV Mobile)
  - 500Â MHz (ULV Mobile) Introduced January 30, 2001
  - 600Â MHz (ULV Mobile)

XScale (chronological entry - non-x86 architecture)

Introduced August 23, 2000
See main entry

Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)

Introduced April 2000 â€" July 2002
See main entries

Pentium III Tualatin-based

Tualatin â€" 0.13Â Î¼m process technology
- 32 KB L1 cache
- 512KB Advanced Transfer L2 cache
- 133Â MHz system bus clock rate
- Socket 370
- Variants
  - 1.0Â GHz
  - 1.13Â GHz
  - 1.26Â GHz
  - 1.4Â GHz

Celeron (Pentium III Tualatin-based)

Tualatin Celeron â€" 0.13Â Î¼m process technology
- 32 KB L1 cache
- 256 KB Advanced Transfer L2 cache
- 100Â MHz system bus clock rate
- Socket 370
- Family 6 model 11
- Variants
  - 1.0Â GHz
  - 1.1Â GHz
  - 1.2Â GHz
  - 1.3Â GHz
  - 1.4Â GHz

Pentium M

Banias 0.13Â Î¼m process technology
- Introduced March 2003
- 64 KB L1 cache
- 1Â MB L2 cache (integrated)
- Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
- 77 million transistors
- Micro-FCPGA, Micro-FCBGA processor package
- Heart of the Intel mobile Centrino system
- 400Â MHz Netburst-style system bus
- Family 6 model 9
- Variants
  - 900Â MHz (ultra low voltage)
  - 1.0Â GHz (ultra low voltage)
  - 1.1Â GHz (low voltage)
  - 1.2Â GHz (low voltage)
  - 1.3Â GHz
  - 1.4Â GHz
  - 1.5Â GHz
  - 1.6Â GHz
  - 1.7Â GHz
Dothan 0.09Â Î¼m (90 nm) process technology
- Introduced May 2004
- 2Â MB L2 cache
- 140 million transistors
- Revised data prefetch unit
- 400Â MHz Netburst-style system bus
- 21W TDP
- Family 6 model 13
- Variants
  - 1.00Â GHz (Pentium M 723) (ultra low voltage, 5W TDP)
  - 1.10Â GHz (Pentium M 733) (ultra low voltage, 5W TDP)
  - 1.20Â GHz (Pentium M 753) (ultra low voltage, 5W TDP)
  - 1.30Â GHz (Pentium M 718) (low voltage, 10W TDP)
  - 1.40Â GHz (Pentium M 738) (low voltage, 10W TDP)
  - 1.50Â GHz (Pentium M 758) (low voltage, 10W TDP)
  - 1.60Â GHz (Pentium M 778) (low voltage, 10W TDP)
  - 1.40Â GHz (Pentium M 710)
  - 1.50Â GHz (Pentium M 715)
  - 1.60Â GHz (Pentium M 725)
  - 1.70Â GHz (Pentium M 735)
  - 1.80Â GHz (Pentium M 745)
  - 2.00Â GHz (Pentium M 755)
  - 2.10Â GHz (Pentium M 765)
Dothan 533 0.09Â Î¼m (90 nm) process technology
- Introduced Q1 2005
- Same as Dothan except with a 533Â MHz NetBurst-style system bus and 27W TDP
- Variants
  - 1.60Â GHz (Pentium M 730)
  - 1.73Â GHz (Pentium M 740)
  - 1.86Â GHz (Pentium M 750)
  - 2.00Â GHz (Pentium M 760)
  - 2.13Â GHz (Pentium M 770)
  - 2.26Â GHz (Pentium M 780)
Stealey 0.09Â Î¼m (90 nm) process technology
- Introduced Q2 2007
- 512 KB L2, 3W TDP
- Variants
  - 600Â MHz (A100)
  - 800Â MHz (A110)

Celeron M

Banias-512 0.13Â Î¼m process technology
- Introduced March 2003
- 64 KB L1 cache
- 512 KB L2 cache (integrated)
- SSE2 SIMD instructions
- No SpeedStep technology, is not part of the 'Centrino' package
- Family 6 model 9
- Variants
  - 310 â€" 1.20Â GHz
  - 320 â€" 1.30Â GHz
  - 330 â€" 1.40Â GHz
  - 340 â€" 1.50Â GHz
Dothan-1024 90 nm process technology
- 64 KB L1 cache
- 1Â MB L2 cache (integrated)
- SSE2 SIMD instructions
- No SpeedStep technology, is not part of the 'Centrino' package
- Variants
  - 350 â€" 1.30Â GHz
  - 350J â€" 1.30Â GHz, with Execute Disable bit
  - 360 â€" 1.40Â GHz
  - 360J â€" 1.40Â GHz, with Execute Disable bit
  - 370 â€" 1.50Â GHz, with Execute Disable bit
    - Family 6, Model 13, Stepping 8
  - 380 â€" 1.60Â GHz, with Execute Disable bit
  - 390 â€" 1.70Â GHz, with Execute Disable bit
Yonah-1024 65 nm process technology
- 64 KB L1 cache
- 1Â MB L2 cache (integrated)
- SSE3 SIMD instructions, 533Â MHz front-side bus, execute-disable bit
- No SpeedStep technology, is not part of the 'Centrino' package
- Variants
  - 410 â€" 1.46Â GHz
  - 420 â€" 1.60Â GHz,
  - 423 â€" 1.06Â GHz (ultra low voltage)
  - 430 â€" 1.73Â GHz
  - 440 â€" 1.86Â GHz
  - 443 â€" 1.20Â GHz (ultra low voltage)
  - 450 â€" 2.00Â GHz

Intel Core

Yonah 0.065Â Î¼m (65 nm) process technology
- Introduced January 2006
- 533/667Â MHz front side bus
- 2Â MB (Shared on Duo) L2 cache
- SSE3 SIMD instructions
- 31W TDP (T versions)
- Family 6, Model 14
- Variants:
  - Intel Core Duo T2700 2.33Â GHz
  - Intel Core Duo T2600 2.16Â GHz
  - Intel Core Duo T2500 2Â GHz
  - Intel Core Duo T2450 2Â GHz
  - Intel Core Duo T2400 1.83Â GHz
  - Intel Core Duo T2300 1.66Â GHz
  - Intel Core Duo T2050 1.6Â GHz
  - Intel Core Duo T2300e 1.66Â GHz
  - Intel Core Duo T2080 1.73Â GHz
  - Intel Core Duo L2500 1.83Â GHz (low voltage, 15W TDP)
  - Intel Core Duo L2400 1.66Â GHz (low voltage, 15W TDP)
  - Intel Core Duo L2300 1.5Â GHz (low voltage, 15W TDP)
  - Intel Core Duo U2500 1.2Â GHz (ultra low voltage, 9W TDP)
  - Intel Core Solo T1350 1.86Â GHz (533 FSB)
  - Intel Core Solo T1300 1.66Â GHz
  - Intel Core Solo T1200 1.5Â GHz

Dual-Core Xeon LV

Sossaman 0.065Â Î¼m (65 nm) process technology
- Introduced March 2006
- Based on Yonah core, with SSE3 SIMD instructions
- 667Â MHz frontside bus
- 2Â MB Shared L2 cache
- Variants
  - 2.0Â GHz

32-bit processors: NetBurst microarchitecture

Pentium 4

0.18Â Î¼m process technology (1.40 and 1.50Â GHz)
- Introduced November 20, 2000
- L2 cache was 256 KB Advanced Transfer Cache (Integrated)
- Processor Package Style was PGA423, PGA478
- System Bus clock rate 400Â MHz
- SSE2 SIMD Extensions
- 42 million transistors
- Used in desktops and entry-level workstations
0.18Â Î¼m process technology (1.7Â GHz)
- Introduced April 23, 2001
- See the 1.4 and 1.5 chips for details
0.18Â Î¼m process technology (1.6 and 1.8Â GHz)
- Introduced July 2, 2001
- See 1.4 and 1.5 chips for details
- Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
- Power <1 watt in Battery Optimized Mode
- Used in full-size and then light mobile PCs
0.18Â Î¼m process technology Willamette (1.9 and 2.0Â GHz)
- Introduced August 27, 2001
- See 1.4 and 1.5 chips for details
Family 15 model 1
Pentium 4 (2Â GHz, 2.20Â GHz)
- Introduced January 7, 2002
Pentium 4 (2.4Â GHz)
- Introduced April 2, 2002
0.13Â Î¼m process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8(OEM),3.0(OEM) GHz)
- Improved branch prediction and other microcodes tweaks
- 512 KB integrated L2 cache
- 55 million transistors
- 400Â MHz system bus.
Family 15 model 2
0.13Â Î¼m process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06Â GHz)
- 533Â MHz system bus. (3.06 includes Intel's Hyper-Threading technology).
0.13Â Î¼m process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4Â GHz)
- 800Â MHz system bus (all versions include Hyper-Threading)
- 6500 to 10,000 MIPS

Itanium (chronological entry - new non-x86 architecture)

Introduced 2001
See main entry

Xeon

Official designation now Xeon, i.e. not "Pentium 4 Xeon"
Xeon 1.4, 1.5, 1.7Â GHz
- Introduced May 21, 2001
- L2 cache was 256 KB Advanced Transfer Cache (Integrated)
- Processor Package Style was Organic Land Grid Array 603 (OLGA 603)
- System Bus clock rate 400Â MHz
- SSE2 SIMD Extensions
- Used in high-performance and mid-range dual processor enabled workstations
Xeon 2.0Â GHz and up to 3.6Â GHz
- Introduced September 25, 2001

Itanium 2 (chronological entry - new non-x86 architecture)

Introduced July 2002
See main entry

Mobile Pentium 4-M

0.13Â Î¼m process technology
55 million transistors
cache L2 512 KB
BUS a 400Â MHz
Supports up to 1Â GB of DDR 266Â MHz Memory
Supports ACPI 2.0 and APM 1.2 System Power Management
1.3 V â€" 1.2 V (SpeedStep)
Power: 1.2Â GHz 20.8 W, 1.6Â GHz 30 W, 2.6Â GHz 35 W
Sleep Power 5 W (1.2 V)
Deeper Sleep Power = 2.9 W (1.0 V)
- 1.40Â GHz â€" 23 April 2002
- 1.50Â GHz â€" 23 April 2002
- 1.60Â GHz â€" 4 March 2002
- 1.70Â GHz â€" 4 March 2002
- 1.80Â GHz â€" 23 April 2002
- 1.90Â GHz â€" 24 June 2002
- 2.00Â GHz â€" 24 June 2002
- 2.20Â GHz â€" 16 September 2002
- 2.40Â GHz â€" 14 January 2003
- 2.50Â GHz â€" 16 April 2003
- 2.60Â GHz â€" 11 June 2003

Pentium 4 EE

Introduced September 2003
EE = "Extreme Edition"
Built from the Xeon's "Gallatin" core, but with 2Â MB cache

Pentium 4E

Introduced February 2004
built on 0.09Â Î¼m (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1Â MB L2 cache
533Â MHz system bus (2.4A and 2.8A only)
800Â MHz system bus (all other models)
125 million transistors in 1Â MB Models
169 million transistors in 2Â MB Models
Hyper-Threading support is only available on CPUs using the 800Â MHz system bus.
The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater bandwidth.
7500 to 11,000 MIPS
LGA 775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64)
The 6xx series has 2Â MB L2 cache and Intel 64

64-bit processors: IA-64

New instruction set, not at all related to x86.
Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly (see its 2001 market reception and 2006 architectural changes).

Itanium

Code name Merced
Family 7
Released May 29, 2001
733Â MHz and 800Â MHz
2MB cache
All recalled and replaced by Itanium 2

Itanium 2

Family 0x1F
Released July 2002
900Â MHz â€" 1.6Â GHz
McKinley 900Â MHz 1.5 MB cache, Model 0x0
McKinley 1Â GHz, 3 MB cache, Model 0x0
Deerfield 1Â GHz, 1.5 MB cache, Model 0x1
Madison 1.3Â GHz, 3 MB cache, Model 0x1
Madison 1.4Â GHz, 4 MB cache, Model 0x1
Madison 1.5Â GHz, 6 MB cache, Model 0x1
Madison 1.67Â GHz, 9 MB cache, Model 0x1
Hondo 1.4Â GHz, 4 MB cache, dual-core MCM, Model 0x1

64-bit processors: Intel 64 â€" NetBurst microarchitecture

Intel Extended Memory 64 Technology
Mostly compatible with AMD's AMD64 architecture
Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)

Pentium 4F

Prescott-2M built on 0.09Â Î¼m (90 nm) process technology
2.8â€"3.8Â GHz (model numbers 6x0)
Introduced February 20, 2005
Same features as Prescott with the addition of:
- 2Â MB cache
- Intel 64-bit
- Enhanced Intel SpeedStep Technology (EIST)
Cedar Mill built on 0.065Â Î¼m (65 nm) process technology
3.0â€"3.6Â GHz (model numbers 6x1)
Introduced January 16, 2006
Die shrink of Prescott-2M
Same features as Prescott-2M
Family 15 Model 4

Pentium D

Dual-core microprocessor
No Hyper-Threading
800(4Ã—200) MHz front side bus
LGA 775 (Socket T)
Smithfield â€" 90 nm process technology (2.66â€"3.2Â GHz)
- Introduced May 26, 2005
- 2.66â€"3.2Â GHz (model numbers 805â€"840)
- 230 million transistors
- 1Â MB Ã— 2 (non-shared, 2Â MB total) L2 cache
- Cache coherency between cores requires communication over the FSB
- Performance increase of 60% over similarly clocked Prescott
- 2.66Â GHz (533Â MHz FSB) Pentium D 805 introduced December 2005
- Contains 2x Prescott dies in one package
- Family 15 Model 4
Presler â€" 65 nm process technology (2.8â€"3.6Â GHz)
- Introduced January 16, 2006
- 2.8â€"3.6Â GHz (model numbers 915â€"960)
- 376 million transistors
- 2Â MB Ã— 2 (non-shared, 4Â MB total) L2 cache
- Contains 2x Cedar Mill dies in one package
- Variants
  - Pentium D 945

Pentium Extreme Edition

Dual-core microprocessor
Enabled Hyper-Threading
800(4Ã—200) MHz front side bus
Smithfield â€" 90 nm process technology (3.2Â GHz)
- Variants
  - Pentium 840 EE â€" 3.20Â GHz (2 Ã— 1Â MB L2)
Presler â€" 65 nm process technology (3.46, 3.73)
- 2Â MB Ã— 2 (non-shared, 4Â MB total) L2 cache
- Variants
  - Pentium 955 EE â€" 3.46Â GHz, 1066Â MHz front side bus
  - Pentium 965 EE â€" 3.73Â GHz, 1066Â MHz front side bus
  - Pentium 969 EE â€" 3.73Â GHz, 1066Â MHz front side bus

Xeon

Nocona
- Introduced 2004
Irwindale
- Introduced 2004
Cranford
- Introduced April 2005
- MP version of Nocona
Potomac
- Introduced April 2005
- Cranford with 8Â MB of L3 cache
Paxville DP (2.8Â GHz)
- Introduced October 10, 2005
- Dual-core version of Irwindale, with 4Â MB of L2 Cache (2Â MB per core)
- 2.8Â GHz
- 800 MT/s front side bus
Paxville MP â€" 90Â nm process (2.67 â€" 3.0Â GHz)
- Introduced November 1, 2005
- Dual-core Xeon 7000 series
- MP-capable version of Paxville DP
- 2Â MB of L2 Cache (1Â MB per core) or 4Â MB of L2 (2Â MB per core)
- 667 MT/s FSB or 800 MT/s FSB
Dempsey â€" 65Â nm process (2.67 â€" 3.73Â GHz)
- Introduced May 23, 2006
- Dual-core Xeon 5000 series
- MP version of Presler
- 667 MT/s or 1066 MT/s FSB
- 4Â MB of L2 Cache (2Â MB per core)
- LGA 771 (Socket J).
Tulsa â€" 65Â nm process (2.5 â€" 3.4Â GHz)
- Introduced August 29, 2006
- Dual-core Xeon 7100-series
- Improved version of Paxville MP
- 667 MT/s or 800 MT/s FSB

64-bit processors: Intel 64 â€" Core microarchitecture

Woodcrest â€" 65 nm process technology
- Server and Workstation CPU (SMP support for dual CPU system)
- Introduced June 26, 2006
- Dual-core
- Intel VT-x, multiple OS support
- EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160
- Execute Disable Bit
- TXT, enhanced security hardware extensions
- SSSE3 SIMD instructions
- iAMT2 (Intel Active Management Technology), remotely manage computers
- Variants
  - Xeon 5160 â€" 3.00Â GHz (4Â MB L2, 1333Â MHz FSB, 80 W)
  - Xeon 5150 â€" 2.66Â GHz (4Â MB L2, 1333Â MHz FSB, 65 W)
  - Xeon 5140 â€" 2.33Â GHz (4Â MB L2, 1333Â MHz FSB, 65 W)
  - Xeon 5130 â€" 2.00Â GHz (4Â MB L2, 1333Â MHz FSB, 65 W)
  - Xeon 5120 â€" 1.86Â GHz (4Â MB L2, 1066Â MHz FSB, 65 W)
  - Xeon 5110 â€" 1.60Â GHz (4Â MB L2, 1066Â MHz FSB, 65 W)
  - Xeon 5148LV â€" 2.33Â GHz (4Â MB L2, 1333Â MHz FSB, 40 W) (low voltage edition)
Clovertown â€" 65 nm process technology
- Server and Workstation CPU (SMP support for dual CPU system)
- Introduced December 13, 2006
- Quad-core
- Intel VT-x, multiple OS support
- EIST (Enhanced Intel SpeedStep Technology) in E5365, L5335
- Execute Disable Bit
- TXT, enhanced security hardware extensions
- SSSE3 SIMD instructions
- iAMT2 (Intel Active Management Technology), remotely manage computers
- Variants
  - Xeon X5355 â€" 2.66Â GHz (2Ã—4Â MB L2, 1333Â MHz FSB, 105 W)
  - Xeon E5345 â€" 2.33Â GHz (2Ã—4Â MB L2, 1333Â MHz FSB, 80 W)
  - Xeon E5335 â€" 2.00Â GHz (2Ã—4Â MB L2, 1333Â MHz FSB, 80 W)
  - Xeon E5320 â€" 1.86Â GHz (2Ã—4Â MB L2, 1066Â MHz FSB, 65 W)
  - Xeon E5310 â€" 1.60Â GHz (2Ã—4Â MB L2, 1066Â MHz FSB, 65 W)
  - Xeon L5320 â€" 1.86Â GHz (2Ã—4Â MB L2, 1066Â MHz FSB, 50 W) (low voltage edition)

Intel Core 2

Conroe â€" 65 nm process technology
- Desktop CPU (SMP support restricted to 2 CPUs)
- Two cores on one die
- Introduced July 27, 2006
- SSSE3 SIMD instructions
- 291 million transistors
- 64 KB of L1 cache per core (32+32 KB 8-way)
- Intel VT-x, multiple OS support
- TXT, enhanced security hardware extensions
- Execute Disable Bit
- EIST (Enhanced Intel SpeedStep Technology)
- iAMT2 (Intel Active Management Technology), remotely manage computers
- LGA 775
- Variants
  - Core 2 Duo E6850 â€" 3.00Â GHz (4Â MB L2, 1333Â MHz FSB)
  - Core 2 Duo E6800 â€" 2.93Â GHz (4Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E6750 â€" 2.67Â GHz (4Â MB L2, 1333Â MHz FSB, 65W)
  - Core 2 Duo E6700 â€" 2.67Â GHz (4Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E6600 â€" 2.40Â GHz (4Â MB L2, 1066Â MHz FSB, 65W)
  - Core 2 Duo E6550 â€" 2.33Â GHz (4Â MB L2, 1333Â MHz FSB)
  - Core 2 Duo E6420 â€" 2.13Â GHz (4Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E6400 â€" 2.13Â GHz (2Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E6320 â€" 1.86Â GHz (4Â MB L2, 1066Â MHz FSB) Family 6, Model 15, Stepping 6
  - Core 2 Duo E6300 â€" 1.86Â GHz (2Â MB L2, 1066Â MHz FSB)
Conroe XE â€" 65 nm process technology
- Desktop Extreme Edition CPU (SMP support restricted to 2 CPUs)
- Introduced July 27, 2006
- same features as Conroe
- LGA 775
- Variants
  - Core 2 Extreme X6800 â€" 2.93Â GHz (4Â MB L2, 1066Â MHz FSB)
Allendale â€" 65 nm process technology
- Desktop CPU (SMP support restricted to 2 CPUs)
- Two CPUs on one die
- Introduced January 21, 2007
- SSSE3 SIMD instructions
- 167 million transistors
- TXT, enhanced security hardware extensions
- Execute Disable Bit
- EIST (Enhanced Intel SpeedStep Technology)
- iAMT2 (Intel Active Management Technology), remotely manage computers
- LGA 775
- Variants
  - Core 2 Duo E4700 â€" 2.60Â GHz (2Â MB L2, 800Â MHz FSB)
  - Core 2 Duo E4600 â€" 2.40Â GHz (2Â MB L2, 800Â MHz FSB)
  - Core 2 Duo E4500 â€" 2.20Â GHz (2Â MB L2, 800Â MHz FSB)
  - Core 2 Duo E4400 â€" 2.00Â GHz (2Â MB L2, 800Â MHz FSB)
  - Core 2 Duo E4300 â€" 1.80Â GHz (2Â MB L2, 800Â MHz FSB) Family 6, Model 15, Stepping 2
Merom â€" 65 nm process technology
- Mobile CPU (SMP support restricted to 2 CPUs)
- Introduced July 27, 2006
- Family 6, Model 15
- same features as Conroe
- Socket M / Socket P
- Variants
  - Core 2 Duo T7800 â€" 2.60Â GHz (4Â MB L2, 800Â MHz FSB) (Santa Rosa platform)
  - Core 2 Duo T7700 â€" 2.40Â GHz (4Â MB L2, 800Â MHz FSB)
  - Core 2 Duo T7600 â€" 2.33Â GHz (4Â MB L2, 667Â MHz FSB)
  - Core 2 Duo T7500 â€" 2.20Â GHz (4Â MB L2, 800Â MHz FSB)
  - Core 2 Duo T7400 â€" 2.16Â GHz (4Â MB L2, 667Â MHz FSB)
  - Core 2 Duo T7300 â€" 2.00Â GHz (4Â MB L2, 800Â MHz FSB)
  - Core 2 Duo T7250 â€" 2.00Â GHz (2Â MB L2, 800Â MHz FSB)
  - Core 2 Duo T7200 â€" 2.00Â GHz (4Â MB L2, 667Â MHz FSB)
  - Core 2 Duo T7100 â€" 1.80Â GHz (2Â MB L2, 800Â MHz FSB)
  - Core 2 Duo T5600 â€" 1.83Â GHz (2Â MB L2, 667Â MHz FSB) Family 6, Model 15, Stepping 6
  - Core 2 Duo T5550 â€" 1.83Â GHz (2Â MB L2, 667Â MHz FSB, no VT)
  - Core 2 Duo T5500 â€" 1.66Â GHz (2Â MB L2, 667Â MHz FSB, no VT)
  - Core 2 Duo T5470 â€" 1.60Â GHz (2Â MB L2, 800Â MHz FSB, no VT) Family 6, Model 15, Stepping 13
  - Core 2 Duo T5450 â€" 1.66Â GHz (2Â MB L2, 667Â MHz FSB, no VT)
  - Core 2 Duo T5300 â€" 1.73Â GHz (2Â MB L2, 533Â MHz FSB, no VT)
  - Core 2 Duo T5270 â€" 1.40Â GHz (2Â MB L2, 800Â MHz FSB, no VT)
  - Core 2 Duo T5250 â€" 1.50Â GHz (2Â MB L2, 667Â MHz FSB, no VT)
  - Core 2 Duo T5200 â€" 1.60Â GHz (2Â MB L2, 533Â MHz FSB, no VT)
  - Core 2 Duo L7500 â€" 1.60Â GHz (4Â MB L2, 800Â MHz FSB) (low voltage)
  - Core 2 Duo L7400 â€" 1.50Â GHz (4Â MB L2, 667Â MHz FSB) (low voltage)
  - Core 2 Duo L7300 â€" 1.40Â GHz (4Â MB L2, 800Â MHz FSB) (low voltage)
  - Core 2 Duo L7200 â€" 1.33Â GHz (4Â MB L2, 667Â MHz FSB) (low voltage)
  - Core 2 Duo U7700 â€" 1.33Â GHz (2Â MB L2, 533Â MHz FSB) (ultra low voltage)
  - Core 2 Duo U7600 â€" 1.20Â GHz (2Â MB L2, 533Â MHz FSB) (ultra low voltage)
  - Core 2 Duo U7500 â€" 1.06Â GHz (2Â MB L2, 533Â MHz FSB) (ultra low voltage)
Kentsfield â€" 65 nm process technology
- Two dual-core CPU dies in one package.
- Desktop CPU quad-core (SMP support restricted to 4 CPUs)
- Introduced December 13, 2006
- same features as Conroe but with 4 CPU cores
- 586 million transistors
- LGA 775
- Family 6, Model 15, Stepping 11
- Variants
  - Core 2 Extreme QX6850 â€" 3Â GHz (2Ã—4Â MB L2 Cache, 1333Â MHz FSB)
  - Core 2 Extreme QX6800 â€" 2.93Â GHz (2Ã—4Â MB L2 Cache, 1066Â MHz FSB) (April 9, 2007)
  - Core 2 Extreme QX6700 â€" 2.66Â GHz (2Ã—4Â MB L2 Cache, 1066Â MHz FSB) (November 14, 2006)
  - Core 2 Quad Q6700 â€" 2.66Â GHz (2Ã—4Â MB L2 Cache, 1066Â MHz FSB) (July 22, 2007)
  - Core 2 Quad Q6600 â€" 2.40Â GHz (2Ã—4Â MB L2 Cache, 1066Â MHz FSB) (January 7, 2007)
Wolfdale â€" 45 nm process technology
- Die shrink of Conroe
- Same features as Conroe with the addition of:
  - 50% more cache, 6Â MB as opposed to 4Â MB
  - Intel Trusted Execution Technology
  - SSE4 SIMD instructions
- 410 million transistors
- Variants
  - Core 2 Duo E8600 â€" 3.33Â GHz (6Â MB L2, 1333Â MHz FSB)
  - Core 2 Duo E8500 â€" 3.16Â GHz (6Â MB L2, 1333Â MHz FSB)
  - Core 2 Duo E8435 â€" 3.07Â GHz (6Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E8400 â€" 3.00Â GHz (6Â MB L2, 1333Â MHz FSB)
  - Core 2 Duo E8335 â€" 2.93Â GHz (6Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E8300 â€" 2.83Â GHz (6Â MB L2, 1333Â MHz FSB)
  - Core 2 Duo E8235 â€" 2.80Â GHz (6Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E8200 â€" 2.66Â GHz (6Â MB L2, 1333Â MHz FSB)
  - Core 2 Duo E8135 â€" 2.66Â GHz (6Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E8190 â€" 2.66Â GHz (6Â MB L2, 1333Â MHz FSB, no TXT, no VT)
Wolfdale-3M â€" 45 nm process technology
- Intel Trusted Execution Technology
- Variants
  - Core 2 Duo E7600 â€" 3.06Â GHz (3Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E7500 â€" 2.93Â GHz (3Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E7400 â€" 2.80Â GHz (3Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E7300 â€" 2.66Â GHz (3Â MB L2, 1066Â MHz FSB)
  - Core 2 Duo E7200 â€" 2.53Â GHz (3Â MB L2, 1066Â MHz FSB)
Yorkfield â€" 45 nm process technology
- Quad-core CPU
- Die shrink of Kentsfield
- Contains 2x Wolfdale dual-core dies in one package
- Same features as Wolfdale
- 820 million transistors
- Variants
  - Core 2 Extreme QX9770 â€" 3.20Â GHz (2Ã—6Â MB L2, 1600Â MHz FSB)
  - Core 2 Extreme QX9650 â€" 3.00Â GHz (2Ã—6Â MB L2, 1333Â MHz FSB)
  - Core 2 Quad Q9705 â€" 3.16Â GHz (2Ã—3Â MB L2, 1333Â MHz FSB)
  - Core 2 Quad Q9700 â€" 3.16Â GHz (2Ã—3Â MB L2, 1333Â MHz FSB)
  - Core 2 Quad Q9650 â€" 3Â GHz (2Ã—6Â MB L2, 1333Â MHz FSB)
  - Core 2 Quad Q9550 â€" 2.83Â GHz (2Ã—6Â MB L2, 1333Â MHz FSB, 95W TDP)
  - Core 2 Quad Q9550s â€" 2.83Â GHz (2Ã—6Â MB L2, 1333Â MHz FSB, 65W TDP)
  - Core 2 Quad Q9450 â€" 2.66Â GHz (2Ã—6Â MB L2, 1333Â MHz FSB, 95W TDP)
  - Core 2 Quad Q9505 â€" 2.83Â GHz (2Ã—3Â MB L2, 1333Â MHz FSB, 95W TDP)
  - Core 2 Quad Q9505s â€" 2.83Â GHz (2Ã—3Â MB L2, 1333Â MHz FSB, 65W TDP)
  - Core 2 Quad Q9500 â€" 2.83Â GHz (2Ã—3Â MB L2, 1333Â MHz FSB, 95W TDP, no TXT)
  - Core 2 Quad Q9400 â€" 2.66Â GHz (2Ã—3Â MB L2, 1333Â MHz FSB, 95W TDP)
  - Core 2 Quad Q9400s â€" 2.66Â GHz (2Ã—3Â MB L2, 1333Â MHz FSB, 65W TDP)
  - Core 2 Quad Q9300 â€" 2.50Â GHz (2Ã—3Â MB L2, 1333Â MHz FSB, 95W TDP)
  - Core 2 Quad Q8400 â€" 2.66Â GHz (2Ã—2Â MB L2, 1333Â MHz FSB, 95W TDP)
  - Core 2 Quad Q8400s â€" 2.66Â GHz (2Ã—2Â MB L2, 1333Â MHz FSB, 65W TDP)
  - Core 2 Quad Q8300 â€" 2.50Â GHz (2Ã—2Â MB L2, 1333Â MHz FSB, 95W TDP)
  - Core 2 Quad Q8300s â€" 2.50Â GHz (2Ã—2Â MB L2, 1333Â MHz FSB, 65W TDP)
  - Core 2 Quad Q8200 â€" 2.33Â GHz (2Ã—2Â MB L2, 1333Â MHz FSB, 95W TDP)
  - Core 2 Quad Q8200s â€" 2.33Â GHz (2Ã—2Â MB L2, 1333Â MHz FSB, 65W TDP)
  - Core 2 Quad Q7600 â€" 2.70Â GHz (2Ã—1Â MB L2, 800Â MHz FSB, no SSE4) (no Q7600 listed here)
Intel Core2 Quad Mobile Processor Family â€" 45 nm process technology
- Quad-core CPU
- Variants
  - Core 2 Quad Q9100 â€" 2.26Â GHz (2Ã—6Â MB L2, 1066Â MHz FSB, 45W TDP)
  - Core 2 Quad Q9000 â€" 2.00Â GHz (2Ã—3Â MB L2, 1066Â MHz FSB, 45W TDP)

Intel Pentium Dual-Core

Allendale â€" 65 nm process technology
- Desktop CPU (SMP support restricted to 2 CPUs)
- Two cores on one die
- Introduced January 21, 2007
- SSSE3 SIMD instructions
- 167 million transistors
- TXT, enhanced security hardware extensions
- Execute Disable Bit
- EIST (Enhanced Intel SpeedStep Technology)
- Variants
  - Intel Pentium E2220 â€" 2.40Â GHz (1Â MB L2, 800Â MHz FSB)
  - Intel Pentium E2200 â€" 2.20Â GHz (1Â MB L2, 800Â MHz FSB)
  - Intel Pentium E2180 â€" 2.00Â GHz (1Â MB L2, 800Â MHz FSB)
  - Intel Pentium E2160 â€" 1.80Â GHz (1Â MB L2, 800Â MHz FSB)
  - Intel Pentium E2140 â€" 1.60Â GHz (1Â MB L2, 800Â MHz FSB)
Wolfdale-3M 45 nm process technology
- Intel Pentium E6800 â€" 3.33Â GHz (2Â MB L2,1066Â MHz FSB)
- Intel Pentium E6700 â€" 3.20Â GHz (2Â MB L2,1066Â MHz FSB)
- Intel Pentium E6600 â€" 3.06Â GHz (2Â MB L2,1066Â MHz FSB)
- Intel Pentium E6500 â€" 2.93Â GHz (2Â MB L2,1066Â MHz FSB)
- Intel Pentium E6300 â€" 2.80Â GHz (2Â MB L2,1066Â MHz FSB)
- Intel Pentium E5800 â€" 3.20Â GHz (2Â MB L2, 800Â MHz FSB)
- Intel Pentium E5700 â€" 3.00Â GHz (2Â MB L2, 800Â MHz FSB)
- Intel Pentium E5500 â€" 2.80Â GHz (2Â MB L2, 800Â MHz FSB)
- Intel Pentium E5400 â€" 2.70Â GHz (2Â MB L2, 800Â MHz FSB)
- Intel Pentium E5300 â€" 2.60Â GHz (2Â MB L2, 800Â MHz FSB)
- Intel Pentium E5200 â€" 2.50Â GHz (2Â MB L2, 800Â MHz FSB)
- Intel Pentium E2210 â€" 2.20Â GHz (1Â MB L2, 800Â MHz FSB)

Celeron

Allendale â€" 65 nm process technology
- Variants
  - Intel Celeron E1600 â€" 2.40Â GHz (512 KB L2, 800Â MHz FSB)
  - Intel Celeron E1500 â€" 2.20Â GHz (512 KB L2, 800Â MHz FSB)
  - Intel Celeron E1400 â€" 2.00Â GHz (512 KB L2, 800Â MHz FSB)
  - Intel Celeron E1300 â€" 1.80Â GHz (512 KB L2, 800Â MHz FSB) (does it exist?)
  - Intel Celeron E1200 â€" 1.60Â GHz (512 KB L2, 800Â MHz FSB)
Wolfdale-3M â€" 45 nm process technology
- Variants
  - Intel Celeron E3500 â€" 2.70Â GHz (1Â MB L2, 800Â MHz FSB)
  - Intel Celeron E3400 â€" 2.60Â GHz (1Â MB L2, 800Â MHz FSB)
  - Intel Celeron E3300 â€" 2.50Â GHz (1Â MB L2, 800Â MHz FSB)
  - Intel Celeron E3200 â€" 2.40Â GHz (1Â MB L2, 800Â MHz FSB)
Conroe-L â€" 65 nm process technology
- Variants
  - Intel Celeron 450 â€" 2.20Â GHz (512 KB L2, 800Â MHz FSB)
  - Intel Celeron 440 â€" 2.00Â GHz (512 KB L2, 800Â MHz FSB)
  - Intel Celeron 430 â€" 1.80Â GHz (512 KB L2, 800Â MHz FSB)
  - Intel Celeron 420 â€" 1.60Â GHz (512 KB L2, 800Â MHz FSB)
  - Intel Celeron 220 â€" 1.20Â GHz (512 KB L2, 533Â MHz FSB)
Conroe-CL â€" 65 nm process technology
- LGA 771 package
- Variants
  - Intel Celeron 445 â€" 1.87Â GHz (512 KB L2, 1066Â MHz FSB)

Celeron M

Merom-L 65 nm process technology
- 64 KB L1 cache
- 1Â MB L2 cache (integrated)
- SSE3 SIMD instructions, 533Â MHz/667Â MHz front-side bus, execute-disable bit, 64-bit
- No SpeedStep technology, is not part of the 'Centrino' package
- Variants
  - 520 â€" 1.60Â GHz
  - 530 â€" 1.73Â GHz
  - 540 â€" 1.86Â GHz
  - 550 â€" 2.00Â GHz
  - 560 â€" 2.13Â GHz
  - 570 â€" 2.26Â GHz

667Â MHz FSB

575 â€" 2.00Â GHz
585 â€" 2.16Â GHz

64-bit processors: Intel 64 â€" Nehalem microarchitecture

Intel Pentium

Clarkdale â€" 32 nm process technology
- 2 physical cores/2 threads
- 3Â MB L3 cache
- Introduced January 2010
- Socket 1156 LGA
- 2-channel DDR3
- Integrated HD GPU
- Variants
  - G6950 â€" 2.8Â GHz (no Hyper-Threading)
  - G6960 â€" 2.933Â GHz (no Hyper-Threading)

Core i3

Clarkdale â€" 32 nm process technology
- 2 physical cores/4 threads
- 64 Kb L1 cache
- 512 Kb L2 cache
- 4Â MB L3 cache
- Introduced in January 7, 2010
- Socket 1156 LGA
- 2-channel DDR3
- Integrated HD GPU
- Variants
  - 530 â€" 2.93Â GHz Hyper-Threading
  - 540 â€" 3.06Â GHz Hyper-Threading
  - 550 â€" 3.2Â GHz Hyper-Threading
  - 560 â€" 3.33Â GHz Hyper-Threading

Core i5

Lynnfield â€" 45 nm process technology
- 4 physical cores
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 8Â MB common L3 cache
- Introduced September 8, 2009
- Family 6 Model E (Ext. Model 1E)
- Socket 1156 LGA
- 2-channel DDR3
- Variants
  - 750S â€" 2.40Â GHz/3.20Â GHz Turbo Boost
  - 750 â€" 2.66Â GHz/3.20Â GHz Turbo Boost
  - 760 â€" 2.80Â GHz/3.33Â GHz Turbo Boost
Clarkdale â€" 32 nm process technology
- 2 physical cores/4 threads
- 64 Kb L1 cache
- 512 Kb L2 cache
- 4Â MB L3 cache
- Introduced January, 2010
- Socket 1156 LGA
- 2-channel DDR3
- Integrated HD GPU
- AES Support
- Variants
  - 650/655K â€" 3.2Â GHz Hyper-Threading Turbo Boost
  - 660/661 â€" 3.33Â GHz Hyper-Threading Turbo Boost
  - 670 â€" 3.46Â GHz Hyper-Threading Turbo Boost
  - 680 â€" 3.60Â GHz Hyper-Threading Turbo Boost

Core i7

Bloomfield â€" 45 nm process technology
- 4 physical cores
- 256 KB L2 cache
- 8Â MB L3 cache
- Front side bus replaced with QuickPath up to 6.4GT/s
- Hyper-Threading is again included. This had previously been removed at the introduction of Core line
- 781 million transistors
- Intel Turbo Boost Technology
- TDP 130W
- Introduced November 17, 2008
- Socket 1366 LGA
- 3-channel DDR3
- Variants
  - 975 (extreme edition) â€" 3.33Â GHz/3.60Â GHz Turbo Boost
  - 965 (extreme edition) â€" 3.20Â GHz/3.46Â GHz Turbo Boost
  - 960 â€" 3.20Â GHz/3.46Â GHz Turbo Boost
  - 950 â€" 3.06Â GHz/3.33Â GHz Turbo Boost
  - 940 â€" 2.93Â GHz/3.20Â GHz Turbo Boost
  - 930 â€" 2.80Â GHz/3.06Â GHz Turbo Boost
  - 920 â€" 2.66Â GHz/2.93Â GHz Turbo Boost
Lynnfield â€" 45 nm process technology
- 4 physical cores
- 256 KB L2 cache
- 8Â MB L3 cache
- No QuickPath, instead compatible with slower DMI interface
- Hyper-Threading is included
- Introduced September 8, 2009
- Socket 1156 LGA
- 2-channel DDR3
- Variants
  - 880 â€" 3.06Â GHz/3.73Â GHz Turbo Boost (TDP 95W)
  - 870/875K â€" 2.93Â GHz/3.60Â GHz Turbo Boost (TDP 95W)
  - 870S â€" 2.67Â GHz/3.60Â GHz Turbo Boost (TDP 82W)
  - 860 â€" 2.80Â GHz/3.46Â GHz Turbo Boost (TDP 95W)
  - 860S â€" 2.53Â GHz/3.46Â GHz Turbo Boost (TDP 82W)

TODO: Westmere

Gulftown â€" 32 nm process technology
- 6 physical cores
- 256 KB L2 cache
- 12Â MB L3 cache
- Front side bus replaced with QuickPath up to 6.4GT/s
- Hyper-Threading is included
- Intel Turbo Boost Technology
- Socket 1366 LGA
- TDP 130W
- Introduced 16 March 2010
- Variants
  - 990X Extreme Edition â€" 3.46Â GHz/3.73Â GHz Turbo Boost
  - 980X Extreme Edition â€" 3.33Â GHz/3.60Â GHz Turbo Boost
  - 970 â€" 3.20Â GHz/3.46Â GHz Turbo Boost
Clarksfield â€" Intel Core i7 Mobile Processor Family â€" 45 nm process technology
- 4 physical cores
- Hyper-Threading is included
- Intel Turbo Boost Technology
- Variants
  - 940XM Extreme Edition â€" 2.13Â GHz/3.33Â GHz Turbo Boost (8Â MB L3, TDP 55W)
  - 920XM Extreme Edition â€" 2.00Â GHz/3.20Â GHz Turbo Boost (8Â MB L3, TDP 55W)
  - 840QM â€" 1.86Â GHz/3.20Â GHz Turbo Boost (8Â MB L3, TDP 45W)
  - 820QM â€" 1.73Â GHz/3.06Â GHz Turbo Boost (8Â MB L3, TDP 45W)
  - 740QM â€" 1.73Â GHz/2.93Â GHz Turbo Boost (6Â MB L3, TDP 45W)
  - 720QM â€" 1.60Â GHz/2.80Â GHz Turbo Boost (6Â MB L3, TDP 45W)

Xeon

Gainestown â€" 45 nm process technology
- Same processor dies as Bloomfield
- 256 KB L2 cache
- 8Â MB L3 cache, 4MB may be disabled
- QuickPath up to 6.4GT/s
- Hyper-Threading is included in some models
- 781 million transistors
- Introduced March 29, 2009
- Variants
  - W5590,X5570, X5570, X5560, X5550, E5540, E5530, L5530, E5520, L5520, L5518 â€" 4 cores, 8Â MB L3 cache, HT
  - E5506, L5506, E5504 â€" 4 cores, 4Â MB L3 cache, no HT
  - L5508, E5502, E5502 â€" 2 cores, 4Â MB L3 cache, no HT

64-bit processors: Intel 64 â€" Sandy Bridge / Ivy Bridge microarchitecture

Celeron

Sandy Bridge â€" 32 nm process technology
- 2 physical cores/2 threads (500 series), 1 physical core/1 thread (model G440) or 1 physical core/2 threads (models G460 & G465)
- 2Â MB L3 cache (500 series), 1Â MB (model G440) or 1.5Â MB (models G460 & G465)
- Introduced 3rd quarter, 2011
- Socket 1155 LGA
- 2-channel DDR3-1066
- 400 series has max TDP of 35Â W
- 500-series variants ending in 'T' have a peak TDP of 35Â W, others â€" 65Â W
- Integrated GPU
  - All variants have peak GPU turbo frequencies of 1Â GHz
  - Variants in the 400 series have GPUs running at a base frequency of 650Â MHz
  - Variants in the 500 series ending in 'T' have GPUs running at a base frequency of 650Â MHz; others at 850Â MHz
  - All variants have 6 GPU execution units
- Variants
  - G440 â€" 1.6Â GHz
  - G460 â€" 1.8Â GHz
  - G465 â€" 1.9Â GHz
  - G530T â€" 2.0Â GHz
  - G540T â€" 2.1Â GHz
  - G550T â€" 2.2Â GHz
  - G530 â€" 2.4Â GHz
  - G540 â€" 2.5Â GHz
  - G550 â€" 2.6Â GHz
  - G555 â€" 2.7Â GHz

Pentium

Sandy Bridge â€" 32 nm process technology
- 2 physical cores/2 threads
- 3Â MB L3 cache
- 624 million transistors
- Introduced May, 2011
- Socket 1155 LGA
- 2-channel DDR3-1333 (800 series) or DDR3-1066 (600 series)
- Variants ending in 'T' have a peak TDP of 35Â W, others 65Â W
- Integrated GPU (HD 2000)
  - All variants have peak GPU turbo frequencies of 1.1Â GHz
  - Variants ending in 'T' have GPUs running at a base frequency of 650Â MHz; others at 850Â MHz
  - All variants have 6 GPU execution units
- Variants
  - G620T â€" 2.2Â GHz
  - G630T â€" 2.3Â GHz
  - G640T â€" 2.4Â GHz
  - G645T â€" 2.5Â GHz
  - G860T â€" 2.6Â GHz
  - G620 â€" 2.6Â GHz
  - G622 â€" 2.6Â GHz
  - G630 â€" 2.7Â GHz
  - G632 â€" 2.7Â GHz
  - G640 â€" 2.8Â GHz
  - G840 â€" 2.8Â GHz
  - G645 â€" 2.9Â GHz
  - G850 â€" 2.9Â GHz
  - G860 â€" 3.0Â GHz
  - G870 â€" 3.1Â GHz
Ivy Bridge â€" 22 nm Tri-gate transistor process technology
- 2 physical cores/2 threads
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 3Â MB L3 cache
- Introduced September, 2012
- Socket 1155 LGA
- 2-channel DDR3-1333 for G2000 series
- 2-channel DDR3-1600 for G2100 series
- All variants have GPU base frequencies of 650Â MHz and peak GPU turbo frequencies of 1.05Â GHz
- Variants ending in 'T' have a peak TDP of 35Â W, others â€" TDP of 55Â W
- Variants
  - G2020T â€" 2.5Â GHz
  - G2030T â€" 2.6Â GHz
  - G2100T â€" 2.6Â GHz
  - G2120T â€" 2.7Â GHz
  - G2020 â€" 2.9Â GHz
  - G2030 â€" 3.0Â GHz
  - G2120 â€" 3.1Â GHz
  - G2130 â€" 3.2Â GHz
  - G2140 â€" 3.3Â GHz

Core i3

Sandy Bridge â€" 32 nm process technology
- 2 physical cores/4 threads
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 3Â MB L3 cache
- 624 million transistors
- Introduced January, 2011
- Socket 1155 LGA
- 2-channel DDR3-1333
- Variants ending in 'T' have a peak TDP of 35Â W, others 65Â W
- Integrated GPU
  - All variants have peak GPU turbo frequencies of 1.1Â GHz
  - Variants ending in 'T' have GPUs running at a base frequency of 650Â MHz; others at 850Â MHz
  - Variants ending in '5' have Intel HD Graphics 3000 (12 execution units); others have Intel HD Graphics 2000 (6 execution units)
- Variants
  - i3-2100T â€" 2.5Â GHz
  - i3-2120T â€" 2.6Â GHz
  - i3-2100 â€" 3.1Â GHz
  - i3-2102 â€" 3.1Â GHz
  - i3-2105 â€" 3.1Â GHz
  - i3-2120 â€" 3.3Â GHz
  - i3-2125 â€" 3.3Â GHz
  - i3-2130 â€" 3.4Â GHz
Ivy Bridge â€" 22 nm Tri-gate transistor process technology
- 2 physical cores/4 threads
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 3Â MB L3 cache
- Introduced September, 2012
- Socket 1155 LGA
- 2-channel DDR3-1600
- Variants ending in '5' have Intel HD Graphics 4000; others have Intel HD Graphics 2500
- All variants have GPU base frequencies of 650Â MHz and peak GPU turbo frequencies of 1.05Â GHz
- TDP 55Â W
- Variants
  - i3-3220T â€" 2.8Â GHz
  - i3-3240T â€" 2.9Â GHz
  - i3-3210 â€" 3.2Â GHz
  - i3-3220 â€" 3.3Â GHz
  - i3-3225 â€" 3.3Â GHz
  - i3-3240 â€" 3.4Â GHz

Core i5

Sandy Bridge â€" 32 nm process technology
- 4 physical cores/4 threads (except for i5-2390T which has 2 physical cores/4 threads)
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 6Â MB L3 cache (except for i5-2390T which has 3Â MB)
- 995 million transistors
- Introduced January, 2011
- Socket 1155 LGA
- 2-channel DDR3-1333
- Variants ending in 'S' have a peak TDP of 65Â W, others â€" 95Â W except where noted
- Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
- Integrated GPU
  - i5-2500T has a peak GPU turbo frequency of 1.25Â GHz, others 1.1Â GHz
  - Variants ending in 'T' have GPUs running at a base frequency of 650Â MHz; others at 850Â MHz
  - Variants ending in '5' or 'K' have Intel HD Graphics 3000 (12 execution units), except i5-2550K which has no GPU; others have Intel HD Graphics 2000 (6 execution units)
  - Variants ending in 'P' and the i5-2550K have no GPU
- Variants
  - i5-2390T â€" 2.7Â GHz/3.5Â GHz Turbo Boost (35Â W max TDP)
  - i5-2500T â€" 2.3Â GHz/3.3Â GHz Turbo Boost (45Â W max TDP)
  - i5-2400S â€" 2.5Â GHz/3.3Â GHz Turbo Boost
  - i5-2405S â€" 2.5Â GHz/3.3Â GHz Turbo Boost
  - i5-2500S â€" 2.7Â GHz/3.7Â GHz Turbo Boost
  - i5-2300 â€" 2.8Â GHz/3.1Â GHz Turbo Boost
  - i5-2310 â€" 2.9Â GHz/3.2Â GHz Turbo Boost
  - i5-2320 â€" 3.0Â GHz/3.3Â GHz Turbo Boost
  - i5-2380P â€" 3.1Â GHz/3.4Â GHz Turbo Boost
  - i5-2400 â€" 3.1Â GHz/3.4Â GHz Turbo Boost
  - i5-2450P â€" 3.2Â GHz/3.5Â GHz Turbo Boost
  - i5-2500 â€" 3.3Â GHz/3.7Â GHz Turbo Boost
  - i5-2500K â€" 3.3Â GHz/3.7Â GHz Turbo Boost
  - i5-2550K â€" 3.4Â GHz/3.8Â GHz Turbo Boost
Ivy Bridge â€" 22 nm Tri-gate transistor process technology
- 4 physical cores/4 threads (except for i5-3470T which has 2 physical cores/4 threads)
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 6Â MB L3 cache (except for i5-3470T which has 3Â MB)
- Introduced April, 2012
- Socket 1155 LGA
- 2-channel DDR3-1600
- Variants ending in 'S' have a peak TDP of 65Â W, Variants ending in 'T' have a peak TDP of 35 or 45Â W (see variants), others â€" 77Â W except where noted
- Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
- Variants ending in 'P' have no integrated GPU; others have Intel HD Graphics 2500 or Intel HD Graphics 4000 (i5-3475S and i5-3570K only)
- Variants
  - i5-3470T â€" 2.9Â GHz/3.6Â GHz max Turbo Boost (35Â W TDP)
  - i5-3570T â€" 2.3Â GHz/3.3Â GHz max Turbo Boost (45Â W TDP)
  - i5-3330S â€" 2.7Â GHz/3.2Â GHz max Turbo Boost
  - i5-3450S â€" 2.8Â GHz/3.5Â GHz max Turbo Boost
  - i5-3470S â€" 2.9Â GHz/3.6Â GHz max Turbo Boost
  - i5-3475S â€" 2.9Â GHz/3.6Â GHz max Turbo Boost
  - i5-3550S â€" 3.0Â GHz/3.7Â GHz max Turbo Boost
  - i5-3570S â€" 3.1Â GHz/3.8Â GHz max Turbo Boost
  - i5-3330 â€" 3.0Â GHz/3.2Â GHz max Turbo Boost
  - i5-3350P â€" 3.1Â GHz/3.3Â GHz max Turbo Boost (69Â W TDP)
  - i5-3450 â€" 3.1Â GHz/3.5Â GHz max Turbo Boost
  - i5-3470 â€" 3.2Â GHz/3.6Â GHz max Turbo Boost
  - i5-3550 â€" 3.3Â GHz/3.7Â GHz max Turbo Boost
  - i5-3570 â€" 3.4Â GHz/3.8Â GHz max Turbo Boost
  - i5-3570K â€" 3.4Â GHz/3.8Â GHz max Turbo Boost

Core i7

Sandy Bridge â€" 32 nm process technology
- 4 physical cores/8 threads
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 8Â MB L3 cache
- 995 million transistors
- Introduced January, 2011
- Socket 1155 LGA
- 2-channel DDR3-1333
- Variants ending in 'S' have a peak TDP of 65Â W, others â€" 95Â W
- Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
- Integrated GPU
  - All variants have base GPU frequencies of 850Â MHz and peak GPU turbo frequencies of 1.35Â GHz
  - Variants ending in 'K' have Intel HD Graphics 3000 (12 execution units); others have Intel HD Graphics 2000 (6 execution units)
- Variants
  - i7-2600S â€" 2.8Â GHz/3.8Â GHz Turbo Boost
  - i7-2600 â€" 3.4Â GHz/3.8Â GHz Turbo Boost
  - i7-2600K â€" 3.4Â GHz/3.8Â GHz Turbo Boost
  - i7-2700K â€" 3.5Â GHz/3.9Â GHz Turbo Boost
Sandy Bridge-E â€" 32 nm process technology
- Up to 6 physical cores/12 threads depending on model number
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- Up to 20Â MB L3 cache depending on model number
- 2270 million transistors
- Introduced November, 2011
- Socket 2011 LGA
- 4-channel DDR3-1600
- All variants have a peak TDP of 130Â W
- No integrated GPU
- Variants
  - i7-3820 â€" 3.6Â GHz/3.8Â GHz Turbo Boost, 4 cores, 10Â MB L3 cache
  - i7-3930K â€" 3.2Â GHz/3.8Â GHz Turbo Boost, 6 cores, 12Â MB L3 cache
  - i7-3960X â€" 3.3Â GHz/3.9Â GHz Turbo Boost, 6 cores, 15Â MB L3 cache
  - i7-3970X â€" 3.5Â GHz/4.0Â GHz Turbo Boost, 6 cores, 15Â MB L3 cache
Ivy Bridge â€" 22 nm Tri-gate transistor process technology
- 4 physical cores/8 threads
- 32+32 Kb (per core) L1 cache
- 256 Kb (per core) L2 cache
- 8Â MB L3 cache
- Introduced April, 2012
- Socket 1155 LGA
- 2-channel DDR3-1600
- Variants ending in 'S' have a peak TDP of 65Â W, variants ending in 'T' have a peak TDP of 45Â W, others â€" 77Â W
- Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
- Integrated GPU Intel HD Graphics 4000
- Variants
  - i7-3770T â€" 2.5Â GHz/3.7Â GHz Turbo Boost
  - i7-3770S â€" 3.1Â GHz/3.9Â GHz Turbo Boost
  - i7-3770 â€" 3.4Â GHz/3.9Â GHz Turbo Boost
  - i7-3770K â€" 3.5Â GHz/3.9Â GHz Turbo Boost

64-bit processors: Intel 64 â€" Haswell microarchitecture

64-bit processors: Intel 64 â€" Broadwell microarchitecture

Core i5

Broadwell - 14nm process technology
- 4 physical cores/4 threads
- 4MB L3 Cache
- Introduced Q2'15
- Socket 1150 LGA
- 2-channel DDR3L-1333/1600
- Integrated GPU
- Variants
  - i5-5575R - 2.80Â GHz/3.30Â GHz Turbo Boost
  - i5-5675C - 3.10Â GHz/3.60Â GHz Turbo Boost
  - i5-5675R - 3.10Â GHz/3.60Â GHz Turbo Boost

Core i7

Broadwell - 14nm process technology
- 4 physical cores/8 threads
- 6 MB L3 Cache
- Introduced Q2'15
- Socket 1150 LGA
- 2-channel DDR3L-1333/1600
- Integrated GPU
- Variants
  - i7-5775C - 3.30Â GHz/3.70Â GHz Turbo Boost
  - i7-5775R - 3.30Â GHz/3.80Â GHz Turbo Boost

64-bit processors: Intel 64 â€" Skylake microarchitecture

Core i3

Skylake - 14 nm process technology
- 2 physical cores/4 threads
- 3-4 MB L3 Cache
- Introduced Q3'15
- Socket 1151 LGA
- 2-channel DDR3L-1333/1600,DDR4-1866/2133
- Integrated GPU Intel HD Graphics 530 (Only i3-6098P have HD Graphics 510)
- Variants
  - i3-6098P - 3.60Â GHz
  - i3-6100T - 3.20Â GHz
  - i3-6100 - 3.70Â GHz
  - i3-6300T - 3.30Â GHz
  - i3-6300 - 3.80Â GHz
  - i3-6320 - 3.90Â GHz

Core i5

Skylake - 14nm process technology
- 4 physical cores/4 threads
- 6 MB L3 Cache
- Introduced Q3'15
- Socket 1151 LGA
- 2-channel DDR3L-1333/1600,DDR4-1866/2133
- Integrated GPU Intel HD Graphics 530
- Variants
  - i5-6400T - 2.20Â GHz/2.80Â GHz Turbo Boost
  - i5-6400 - 2.70Â GHz/3.30Â GHz Turbo Boost
  - i5-6500T - 2.50Â GHz/3.10Â GHz Turbo Boost
  - i5-6500 - 3.20Â GHz/3.60Â GHz Turbo Boost
  - i5-6600T - 2.70Â GHz/3.50Â GHz Turbo Boost
  - i5-6600 - 3.30Â GHz/3.90Â GHz Turbo Boost
  - i5-6600K - 3.50Â GHz/3.90Â GHz Turbo Boost

Core i7

Skylake - 14nm process technology
- 4 physical cores/8 threads
- 8MB L3 Cache
- Introduced Q3'15
- Socket 1151 LGA
- 2-channel DDR3L-1333/1600,DDR4-1866/2133
- Integrated GPU Intel HD Graphics 530
- Variants
  - i7-6700T - 2.80Â GHz/3.60Â GHz Turbo Boost
  - i7-6700 - 3.40Â GHz/4.00Â GHz Turbo Boost
  - i7-6700K - 4.00Â GHz/4.20Â GHz Turbo Boost
Broadwell-E - 14nm process tecnology
- 6-10 physical cores/12-20 threads
- 15-25 MB L3 Cache
- Introduced Q2'16
- Socket 2011-v3 LGA
- 4-channel DDR4-2133/2400
- No Integrated GPU
- Variants
  - i7-6800K - 3.40Â GHz/3.60Â GHz Turbo Boost/3.80Â GHz Turbo Boost Max Tecnology 3.0 Frequency 15MB L3 Cache
  - i7-6850K - 3.60Â GHz/3.80Â GHz Turbo Boost/4.00Â GHz Turbo Boost Max Tecnology 3.0 Frequency 15MB L3 Cache
  - i7-6900K - 3.20Â GHz/3.70Â GHz Turbo Boost/4.00Â GHz Turbo Boost Max Tecnology 3.0 Frequency 20MB L3 Cache
  - i7-6950X - 3.00Â GHz/3.50Â GHz Turbo Boost/4.00Â GHz Turbo Boost Max Tecnology 3.0 Frequency 25MB L3 Cache

64-bit processors: Intel 64 â€" Kaby Lake microarchitecture

Intel Tera-Scale

2007: Teraflops Research Chip, an 80 cores processor prototype.
2009: Single-chip Cloud Computer, a research microprocessor containing the most Intel Architecture cores ever integrated on a silicon CPU chip â€" 48 cores.

Intel 805xx product codes

Intel discontinued the use of part numbers such as 80486 in the marketing of mainstream x86-architecture microprocessors with the introduction of the Pentium brand in 1993. However, numerical codes, in the 805xx range, continued to be assigned to these processors for internal and part numbering uses. The following is a list of such product codes in numerical order:

Intel 806xx product codes

References

External links

Intel Museum: History of the Microprocessor
Stealey A100 and A110
Intel Product Specifications

Minggu, 16 Juli 2017